A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS

Transient voltage peaking under very fast electrostatic discharge (ESD), like charged device model (CDM) pulse, is a serious problem to integrated circuits (ICs). A combined TCAD simulation and very fast transmission line pulse (VFTLP) testing method is proposed to thoroughly investigate the transient voltage peaking phenomena of diode-based ESD protection structures under CDM stressing. The study of a set of diode, diode-string and diode-triggered silicon-controlled rectifier (DTSCR) ESD protection structures, fabricated in a 28nm CMOS process, reveals that the inductive impedance along the ESD discharging path may be the root cause of voltage peaking under CDM stressing. The observation provides the design insights overcoming the voltage peaking problem in ESD protection designs before complicate CDM package level testing.