Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform Track Resources

Due to the rapid advance of integrated circuit (IC)-related technologies, design complexity is dramatically increasing in printed circuit boards (PCBs). Nowadays, a dense PCB contains thousands of pin shapes and signal nets, and such a huge net count makes the manual design of PCBs an extremely time-consuming task, especially in the routing phase. Bus routing, which consists of assigning all the buses to routing layers and topologically routing them on each layer while satisfying some constraints, is one of the most difficult steps in PCB routing. In addition, to take timing into consideration, all bits of a bus are highly preferred to have approximately the same length which are referred to as the length-matching issue. In advanced technology nodes, moreover, routing tracks are provided to help router adhere to design rules and help mask coloring. In this article, we develop a sophisticated bus router which optimizes routability, wirelength, as well as length-matching while simultaneously considering track resources, obstacles, and other design constraints. Experimental results show that the proposed algorithm flow can outperform the state-of-the-art bus routers in terms of the total routing cost and the min-max length difference for the benchmarks provided by the 2018 CAD contest at ICCAD.