Comparison of Multiplication Algorithms Based on FPGA

The multiplication algorithm has been widely implemented in many computations and tasks. In the multiplication algorithm, the multiplication of two numbers has a characteristic of commutative. It should be understood that the commutative characteristic is just causing a result orientation while both of them have a different concept. Basically, the concept of the multiplication is repeated addition. The multipliers in the digital devices are very complex circuits and high cost. The large value multiplication will consume many additions while the components used in the digital machines are very limited when it is implemented to handle such case that could consume many components. Many algorithms of binary multiplication have been proposed to solve in many implementations in the digital devices. This paper has presented the comparison of the multiplication algorithm of the binary number in the implementation of the FPGAs. The complexity and reduced time have become issues in the implementation of the field programmable gate arrays (FPGAs).