Abstract:
A low-power 2-channel PAM4 transmitter front-end consisting of 65-nm CMOS PAM4 shunt LD drivers and flip-chip-bonded 1.3-μm LD-array-on-Si achieves simultaneous 2ch × 53-...Show MoreMetadata
Abstract:
A low-power 2-channel PAM4 transmitter front-end consisting of 65-nm CMOS PAM4 shunt LD drivers and flip-chip-bonded 1.3-μm LD-array-on-Si achieves simultaneous 2ch × 53-Gps PAM4 transmission over 2-km-long SSMF with power efficiency of 0.57 mW/Gbps.
Date of Conference: 08-12 March 2020
Date Added to IEEE Xplore: 04 May 2020
ISBN Information:
Conference Location: San Diego, CA, USA
Contents 