Empirical Bounds of Multicore Cache Interference for Real-Time Schedulability Analysis

Multicore processors offer significant advantages of weight, power, and space to embedded real-time developers, making their adoption almost inevitable. Also, system sustainability and economies of scale will increasingly make multicore devices indispensable. However, predictability of performance, specifically, establishing realistic upper bounds on execution time for schedulability analysis is a significant challenge to certification. This paper describes a methodology for empirically establishing a reasonable, high-confidence upper bound for cache interference effects in the context of engineering practices commonly used in certifiable real-time systems.