Analysis and Design Implementation of Modulator π/4 – Differential Quadrature Phase Shift Keying Low Power Based on FPGA

Wireless communication systems require peripherals with low power consumption and ease in the process of receiving signals for efficiency purposes. The π/4-DQPSK modulation scheme has an effective demodulation concept because it does not require phase synchronization on the receiving system (non-coherent). This study aims to implement the π/4-DQPSK modulator in full-digital FPGA to increase power efficiency and noise resistance. The experimental hierarchy begins with the design of the modulator simulation on the Simulink Matlab then the next step is the implementation of the Altera Cyclone IV FPGA. Evaluation of the constellation symbol from simulation results and comparison of demodulation outcome with initial input pulses can represent that the π/4-DQPSK modulator architecture is optimal. The application of the π/4-DQPSK modulator on FPGA has produced binary output corresponding to the symbol constellation magnitude value and low BER (Bit Error Rate) performance in the signal-to-noise ratio range of -20dB to 10dB.