Rapid High-Level FPGA Resource Estimation for a Novel Heterogeneous Platform Scheduling Scheme

This paper presents a fast estimation tool of the FPGA resources from a high-level circuit description. The tool has been developed within the context of a heterogeneous scheduling scheme that encompasses the GPU, CPU and FPGA as target devices, but can be used also as a stand-alone tool for design space exploration. The proposed tool is the first to estimate the FPGA resources from OpenCL programmed kernels. Estimates are based on static features extracted at compile time, and testing over several kernels shows high accuracy that meets the requirements of the scheduling scheme with low computational cost.