Simulation Investigation of Halo Surrounding Gate TFET with Stacked Dielectric

This paper describes the novel design for a high k dielectric stacked halo surrounding gate tunnel field effect transistor. The device is explored using realistic device parameters. The device simulation is carried on a numerical device simulating tool, Silvaco ATLAS Technology computer aided design (TCAD). The electric parameters such as surface potential and electric field are analyzed across the channel length of the device structure. The input and output characteristics are studied for halo high-k SG TFET for different bias voltages. Furthermore, the performance of the halo high-k device is compared with the surrounding gate TFETs and stacked high-k SG TFET. The comparison analysis of all the three devices shows a better performance for halo high-k SG TFETs with higher ON current and ${I}_{ON}/{I}_{OFF}$ ratio resulting in promising device for circuit applications with low power and fastest switching.