A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol

This paper presents the first SerDes design to demonstrate a PCI-Express 5 link with area of 0.33mm2 per lane, die edge usage per lane of 285 um, dynamic junction temperature range from -40C to 125C, energy efficiency of 11.4pJ/bit including PLL and clocking, power management including power gating for all analog blocks, continuous data rate support between 1–32 Gb/s, and supporting channel topologies with insertion loss up to 37dB at 16GHz with BER < 1e-12 in 10nm process technology.