A 6-Transistor Ultra-Low Power CMOS Voltage Reference with 0.02%/V Line Sensitivity

This work presents a technique for design of ultralow power (ULP) CMOS voltage references achieving extremely low line sensitivity while maintaining state-of-the-art temperature insensitivity through the use of a 6-transistor (6 T) structure. The proposed technique demonstrates good performance in sub-100 nm CMOS technologies. The 65-nm CMOS implementation occupies only 840 μ m
²
of area and consumes 28.6 pA from a 0.5 V supply. Measurements from 6 samples from the same wafer show an average line sensitivity of 0.02 %/V, a 10X improvement over previous 65 nm implementations, and an average temperature coefficient of 99.2 ppm/°C.