A 0.2-V 10-bit 5-kHz SAR ADC with Dynamic Bulk Biasing and Ultra-Low-Supply-Voltage Comparator

This paper describes a 10-bit 5-kHz SAR ADC under an ultra-low-supply-voltage of 0.2 V for low-power applications. To tolerate the severe variations in the subthreshold regime, a novel dynamic bulk biasing circuit senses the NMOS/PMOS strength ratio in the background and applies feedback to recover the circuit functionality. A new comparator relaxes the stringent speed-noise trade-off under the 0.2-V supply. Employing ac-coupling, stacked input pairs, and voltage-boosted load capacitors, the comparator achieves more than threefold improvement in speed with little noise penalty. The measured ADC consumes 22 nW and exhibits an SNDR of 52.8 dB at Nyquist, yielding an FoM of 12.3 fJ/conv.-step. Measurements of multiple chips show the proposed dynamic bulk biasing successfully improves the yield by nearly twofold in the presence of supply variations.