Area and Power Efficient 64-Bit Booth Multiplier

A small chip that can function as an amplifier, oscillator, timer or microprocessor is called an integrated circuit. All the electronic devices such as mobile phones, gaming systems and electronic devices powered by battery uses microelectronic circuits. It produces high power dissipation. As the technology shrinks to 65nm, there is no much increase in dynamic power dissipation but the leakage power increases tremendously. So there is a need for low power techniques to reduce the associated power. This power reduction can be obtained by system or algorithm or architectural level. Booth multiplier has wide application in low power VLSI. It is due its less computation time, low area and less power consumption. This work aims to design a pipelined 64 bit Booth multiplier. In the normal process of reduction of the partial products of binary of radix-16, the maximum height of the column of the partial products is n+1/4 where, n is the unsigned operand. The carry save adders are used for reducing height to n/4. The recoding of the booth multiplier is implemented. In this work carry save adder is replaced by the carry skip adder for reducing the power and area. The power consumption reduced by 11% and the area reduction obtained was 9%.