ASIC Implementation of Pipelined Blowfish Cryptographic Core in 0.13 µm CMOS Process Technology

Cost of data breach is frightfully alarming and software-based solutions for addressing information security may not just be enough. The need for hardware-level cryptography gave rise to the conception of this research aiming at the ASIC implementation of a Blowfish cryptographic core in 0.13 μm CMOS process technology, and at the employment of pipelining and datapath modification to the Blowfish algorithm for propagation delay reduction and performance enhancement. The original 32-bit datapath of the Blowfish algorithm is sectioned to four to arrive at byte-level data processing. Modification to 8-bit datapath reduces the delay associated with 32-bit addition brought by the propagation of carry between full adders. The clock cycle number increase during datapath modification is compensated by pipelining several processes with the application of iterative design which will allow for lesser area during synthesis. The RTL model for the implementation is written in Verilog HDL and the final design after synthesis and optimization yields an operating frequency of up to 425.5319 MHz with a power rating of 5.25 mW and an area of only 928 standard cells.