Analysis and Comparison of Novel Clock Gating Cell Topologies in 65nm CMOS Process Technology

An analysis and comparison of three novel clock gating topologies in the TSMC 65nm CMOS Process Technology is presented in this study. Additional logic is added to these topologies to accommodate a scan-enable signal for future ASIC implementations. In addition to schematic simulations, a standard cell layout of each topology that conforms to the design constraints of the TSMC 65nm Digital Library are designed and simulated. The circuits are tested at 5MHz, 15MHz, and 25MHz input clock frequencies using TT, SS, and FF process corners within a 1V supply voltage. Data is gathered from the simulations using a fair and uniform environment. A ranking system composed of the power consumption, propagation delay, standard cell width, and rise and fall times is utilized as a basis for performance comparison. The results of the comparison serves as a basis for future low-power digital circuits and custom standard cell design and implementation.