FIR Filter Realization Under the Trade-Off Between Implementation Complexity and Computation Rate

We propose a flexible finite impulse response (FIR) filter structure which can avail the benefits of trade-off between computation units and clock rate. For designing such flexible FIR filter, we first present two supporting structures viz., Structure I and Structure II. Structure I realizes the FIR filter via single multiplier, single adder, and N delays, where all units operate at the rate of Nfin (i.e., high clock rate), and N and fin denote the order of FIR filter and input sampling frequency, respectively, whereas Structure II implements the FIR filter using NM multipliers, M N - M2 adders, and M N - M2 delays in the filter unit with clock rate [(fin)/M] (i.e., computationally low-speed realization), and M-1 adders and delays at the output unit operate at fin, where 2 ≤ M ≤ N and M denotes the upsampler/downsampler. Then, we propose Structure III via Structures I & II, which provides the flexible realization of FIR filters under the trade-off between computational units and clock rate. We also analyze the performance of these structures in terms of number of multipliers (CM), number of adders (CA), number of delays (CD), and operating frequency (Fopt) with the help of numerical example in comparison of the direct form FIR filter.