A Diagnosis Pattern Generation Procedure to Distinguish Between Stuck-at and Bridging Faults in Digital Circuits

In the field of VLSI testing, fault diagnosis has become necessary. Though there are different types of faults available, the two commonly used faults are bridging and stuck-at faults. The methods that already exist involve the manual modification of the logical circuit like the addition of gates, multiplexers etc. The proposed work is about creating a pattern generation procedure for distinguishing between stuck-at and bridging faults without altering the circuit under test. The faults are considered in pairs and test patterns are generated accordingly to distinguish between the two faults using ATPG tools. The fault inactivation method has been used to generate the test patterns. Diagnosis patterns are generated that will be capable of individually distinguishing each fault pair in the circuit. Experiments have been conducted on the ISCAS’ 85 benchmark circuits and the number of diagnosis patterns obtained for each fault pair were tabulated. Other important parameters like the number of faults detected, fault coverage, CPU run time etc. were also analysed.