Design of encapsulating materials for advanced area bump packages

At present, over 5 billion IC units are produced every month across the world. Almost all of them are protected from the effects of environmental stresses such as humidity, heat, mechanical stress, and pollution, when installed in actual electronic devices. However, higher frequency and higher I/O trends require shorter electrical pass length in the packages. Flip chip packaging is one of the best solutions for these requirements. Use of this package has been expanding in leading edge microprocessors and peripheral ICs. The next market requirement for the flip chip package is low cost and mass production flip chip packaging for conventional ICs. For the purpose of cost reduction with mass production, transfer molding for flip chip packaging has been studied. Even flow to thin and thick gaps is required for this package and process. By controlling filler particle size, flow balance was well controlled. As a result, good potential for transfer underfill was observed in this study. A plastic substrate is another solution for cost reduction and higher frequency applications. However, there is one major concern in the use of plastic substrates: thermal expansion (CTE) mismatch between substrate and silicon chip, which causes poor thermal shock reliability. The preset underfill with clamping cure process showed improved thermal shock performance for plastic substrate flip chip packages.