6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels

To meet the demand for high memory bandwidth, high-bandwidth memory (HBM) uses a silicon interposer technology to increase the number of I/O pins. Interfaces with the silicon interposer provide a higher throughput (Gb/s/μm) than other packaging technologies due to the high channel density. To increase the throughput further, either the per-pin data rate or the channel density should be increased. Since increasing the per-pin data rate requires a complex and power-hungry circuitry, increasing the channel density is an effective way to achieve the high throughput. However, a main problem with reducing the channel pitch is the crosstalk (XT) between adjacent lanes [1]. If the channels are stacked vertically for high channel density, the vertically adjacent channels become additional XT sources. There have been many research reports on the XT cancellation (XTC) between the printed circuit board (PCB) traces, but only a few have been studied and reported on the XTC between silicon interposer channels. An XTC scheme for an on-chip interconnect, which is similar to the silicon interposer channel was proposed in [2], but it works only for a capacitively driven interconnect. A decision feedback-based XT canceller presented in [3] can cancel the multiple XT lane sources, but it consumes much power because of the large number of feedback taps. This paper presents a high throughput transceiver for HBM with 3D-staggered channels in the silicon interposer. The proposed FFE-combined XTC scheme efficiently compensates for XT from the vertically and horizontally adjacent channels, allowing for high channel density. The transceiver achieves the throughput of (Gb/s/μm) by reducing the channel pitch down to 0.5μm.