31.2 CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems

Annealing processors [1]-[3] based on the convergence property of the Ising model offer an attractive means for solving combinatorial optimization problems [4]. A recently developed annealing processor exploiting the quantum tunneling effect [1] implemented 2048 qubits using 128,000+ Josephson junctions. However, the practical application of quantum annealers is limited by the extremely low temperature (15mK) for operating their superconducting circuits and the associated huge power consumption (25kW). Alternatively, low-power annealing processors [2]-[3] based on the simulated annealing have been developed recently using low-cost CMOS processes. However, previous annealing processors with SRAM-based spin and coefficient memories have limited scalability, and there is a significant room for improvement in energy efficiency and annealing time. In this paper, we propose a scalable annealing processor based on compute-in-memory spin operators and register-based spins, enabling >10× higher energy-efficiency and faster annealing time.