SCA eXtension: a Design for FPGA Parameter Configuration within the ATLAS DAQ Scheme

The foreseen upgrades of the Large Hadron Collider (LHC) are expected to increase the demand in throughput of the front-end and back-end electronics that support the readout of the LHC detectors. Therefore, the complexity of the electronics systems will be increased as well. An example of this is the electronics system of the New Small Wheel (NSW) upgrade of the Toroidal LHC ApparatuS (ATLAS) detector, which will be comprised of a plethora of Field-Programmable Gate Arrays (FPGAs), and Application-Specific Integrated Circuits (ASICs). The Slow Control Adapter eXtension (SCAX) is an FPGA module, designed to support FPGA systems that are part of the ATLAS electronics scheme by writing into the configuration parameters or reading back any of the status registers of their logic. SCAX mimics the I
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C interface of the SCA ASIC used by the NSW ASICs. It thereby enables using the same OPC-UA server and back-end software that support the ASICs. This work describes the context of the SCAX's implementation, as well as architectural considerations of the module and techniques to validate its hardware implementation.