Advanced System in FPGA for 3D (X, Y, t) Imaging with Cross Delay-Lines

In many experiments involving detection of events, information is represented both by position and time of occurrence of the interaction. For the latter, the resolution is a primary demand that must remain compliant with global versatility and fast real-time computing of the system. At the basis of this kind of measurements are detectors providing at the same time X-Y position and the arrival time t of each detected event. Among these detectors, Cross Delay-Lines (CDL) detectors are one of the reference solutions and use the information of detection time also for determining the position of the event. The requests of precise time measurement and fast computing time-resolved experiments are nowadays fulfilled at best by the combination of Time-to-Digital Converter (TDC) architectures with spatial computing environment of Field Programmable Gate Array (FPGA) devices. Although very promising results have been achieved, time resolution necessary to imaging applications is still a serious limiting factor. Starting from a previous system introduced in [5], in which a multi-channel TDC is combined with efficient readout logic to maximize the overall efficiency, we propose a re-design of this system both in the hardware and firmware parts. In particular, the TDC reduces the Integral Non-Linearity error (INL) from 80 ps over 50 ns of full scale-range to 4 ps over 0.5 ms, maintaining resolution up to 1 ps and single-shot precision of the channel lower than 12 ps r.m.s. This has greatly improved the overall performance of the detected image of the CDL detector, allowing a spatial X/Y precision up to 35/50 mm r.m.s. respectively without local aberrations due to the INL.