LDPC Decoder Power Consumption Optimization

The paper presents the results of developing a decoder architecture of low-density parity check code of the DVB-S2 standard for field programmable gate array. It supports several code rates and codeword lengths described in the appendix of the standard. The proposed decoder architecture has a partially parallel structure, which allows to achieve high decoding performance and efficient use of chip area. The presence of double-diagonal submatrices in the structure of the parity check matrices was also confirmed, and a method for eliminating them was implemented. In the work, an analysis of parameters affecting the static and dynamic power consumption in the field programmable gate array was made. Based on it, algorithmic and architectural methods for reducing consumption are proposed. The paper describes the developed architectures and methods to reduce chip power consumption.