An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture

As the first kind of capacity-achieving forward error correction (FEC) codes, polar codes have attracted much research interest recently. Compared with traditional FEC codes, polar codes show better error correction performance when successive cancellation list (SCL) decoding with cyclic redundancy check is adopted. However, its serial decoding nature and high complexity of list management lead to its low throughput. Though the adaptive SCL decoding and hybrid decoding can improve the throughput, it comes at cost of implementation area. In this paper, we propose a pipelined hybrid decoding procedure and the corresponding hardware architecture to improve the area efficiency. In our design, the idle decoding cores are employed for successive cancellation (SC) decoding when SCL decoding is not working. The SCL decoding will be activated when the SC decoding fails. Different decoding cores work according to their own operation sequences and share one common processing array to improve the utilization ratio of processing elements. Constant receiving interval is supported with the design of input buffer to store all received codewords. A software platform is established to optimize the design parameters for each module of decoder. Moreover, the corresponding architecture is implemented using 65nm technology. Experimental results show that the proposed decoder can achieve a similar error correction performance with the SCL decoding with list size 16. Compared to the state-of-the-art available hybrid decoder, our proposed pipelined hybrid decoder is $3.07\times $ more area efficient.