A 110.3-bits/min 8-Ch SSVEP-based Brain-Computer Interface SoC with 87.9% Accuracy

A wearable brain-computer interface (BCI) based on steady-state visual evoked potential (SSVEP) has been widely studied to enable paralyzed patients to communicate with others. However, target identification accuracy and information transfer rate (ITR), which are general performance indicators of SSVEP-based BCI system, still need to be further improved in wearable devices. This paper proposes 8-channel SSVEP-based visual target identification system-on-chip (SoC) to improve the ITR of low-cost wearable BCI device while dramatically reducing the computational complexity without accuracy degradation. The proposed target identification algorithm, CCA-CR, includes algorithmic optimizations and candidate reduction (CR) method that reduce signal processing load by at least 75% without degrading target identification accuracy and ITR. This paper also proposes a matrix decomposition processor (MDP) that calculates complex matrix arithmetic operations through systolic array based CCA-CR engines. Compared to the state-of-the-art CCA-based algorithm, the proposed SoC implemented in FPGA exhibits 63% better ITR with 33% reduction of recording time without accuracy degradation.