FIR Filter Design and Implementation for Phase-Based Processing

Complex steerable pyramid (CSP) is widely used to decompose images into muti-scale and oriented subbands for phase-based processing, such as video magnification, frame interpolation, and view synthesis. The conventional implementation is based on frequency-domain bandpass filtering which relies on fast Fourier transform (FFT). However, FFT requires high-precision computation and complex memory access for hardware implementation. In this paper, we study computation- and memory-efficient finite impulse response filter implementation for CSP. We use Kaiser windowing for filter designs and adopt 9-tap radial and 11-tap angular filters which can achieve 38.6 dB of PSNR for frame interpolation. We then discuss about VLSI architecture designs and, in particular, propose a stripe-based computation flow for 2-D CSP to reduce the line buffer size down to 15%. For evaluation, we implement two VLSI circuits using TSMC 40nm technology. One is a 1-D CSP engine working at 4K UHD 30 fps, and it saves 67.8% of logic gates compared to a FFT-based design. The other is a 2-D CSP engine working at FHD 60 fps. It uses 32-KB SRAM and 3.5M-gate logic. We also implement a FPGA system for 2-D CSP engine, and it operates at 80 MHz and provides 1024×1024 resolution video at 16 fps.