Efficient Implementation of the Data Link Layer at the Receiver of JESD204B

JESD204B is the latest industry standard for the interface between data converters and logic devices. A quad-byte parallel implementation of the data link layer in JESD204B receiver was proposed, a series of data processing, the synchronization control and peripheral auxiliary functions prescribed in JESD204B protocol were implemented. Use of a topological structure for parallel processing control information and data information accelerated the circuit speed and reduced the number of logic layers of synchronization control module; furthermore the theoretical circuit operating clock frequency was reduced from 1.25 GHz to 312.5 MHz which made it easier to be implemented in low-cost CMOS technology. A docking verification between the Verilog model and XLINX's official JESD204B 6.1v receiver IP core was performed, and the simulation results were consistent with the theoretical analysis results; in addition, the design was synthesized with SMIC 180nm CMOS technology at Design Compiler platform, and the synthesis results show that the design fully met the JESD204B protocol specification in operating frequency, cell area and power consumption.