Hardware Implementation of ECIES Protocol on Security SoC

This paper describes a hardware implementation of ECIES (Elliptic Curve Integrated Encryption Scheme) protocol using a security SoC (System on Chip). The security SoC based on Cortex-M0 microcontroller integrates four cryptographic cores including ECC (Elliptic Curve Cryptography) core, SHA3 (Secure Hash Algorithm 3) core, UAAP (United ARIA and AES Processor) core, and TRNG (True Random Number Generator) core, which are connected to AHB-Lite. The ECC core is used for public key generation and key agreement function, and the SHA3 core is used for key derivation function. In addition, the block cipher AES is used for encryption/decryption and CBC-MAC. The security SoC was implemented in FPGA device, and the ECIES protocol was validated by hardware-software co-verification.