Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs

This paper presents experimental characterizations and device modeling on the nanoscale MOSFETs with 40 nm low-power CMOS technology. Systematic temperature-dependent
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results of NMOS/PMOS devices reveal that both the threshold voltage and the effective channel mobility exhibit strong correlations with the device size owning to the depletion region broadening around the gate channel at cryogenic temperatures. By taking the temperature-driven gate geometry effects into consideration, a generic physical model with universal fitting parameters is proposed to depict the transfer characteristics of all CMOS transistors across the device size chart, and further validations of the modified BSIM compact model might pave the way for an accurate design of cryogenic electronics applications.