A −193.6 dBc/Hz FoMT 28.6-to-36.2 GHz Dual-Core CMOS VCO for 5G Applications

By combining the transformer feedback and VCO multi-core techniques, this paper presents a 0.5 V low voltage 28.6-to-36.2 GHz dual-core VCO for 5G applications. Based on the transformer feedback topology, with the power-ground interconnect inductor and embedded decouple capacitor, the second harmonic real impedance is achieved at the VCO cross-couple pair source terminal. Accordingly, the common-mode current path is reduced and the signal symmetry improved, suppressing the flicker noise up conversion. With a 4 bit switch capacitors and varactors, the proposed VCO achieves a 28.6-to-36.2 GHz (23.5 %) tuning range, and its flicker noise corner is from 250 to 980 kHz. Fabricated in a 65nm CMOS process, the VCO consumes 4.6mW from a 0.5 V supply voltage with a core area of about $0.24\times 0.5$ mm
²
. At 31 GHz, the proposed VCO achieves a phase noise of -103 dBc/Hz@1MHz offset, resulting in a figure-of-merit (FoM) of -186.2 dBc/Hz and tuning range figure-of-merit (FoMT) of -193.6 dBc/Hz, respectively.