Compact Simulation of Chip-to-Chip Active Noise Coupling on a System PCB Board

A chip-to-chip active noise coupling demonstrator integrates two identical complementary metal oxide silicon (CMOS) chips on a printed circuit board (PCB), where each chip has the capability of power noise generation by CMOS shift resister array circuits (noise source; NS) and also power noise measurements by on-chip voltage monitoring circuits (OCM). For establishing the noise aware design strategy and methodology, a full-system level noise coupling simulation technique is evaluated on the demonstrator representing a multi-chip mixed-signal PCB. In an experimental scenario, an IC chip (Aggressor IC) operates the NS to generate power noise and the OCM measures the voltage fluctuation of the power delivery network (PDN) within the chip. On the other hand, another IC (Victim IC) holds the NS in no operation while uses the OCM to monitor its PDN voltage fluctuation caused by the conducted noise from the aggressor IC. For the verification of simulation accuracy, two chip power models (CPM), package wire models, discrete de-cap models and a single PCB model are combined into a chip-package-system (CPS) integrated model. The simulation was performed in about 2 hours for CPS integrated noise simulation including S-parameter extraction of the PCB. It is demonstrated that the full-system model with the two CPMs successfully simulates chip-to-chip active noise coupling, namely noise propagation from internal circuits of an aggressor chip to those on a victim chip. The chip-to-chip noise coupling simulation exhibited good agreements with measurements in case studies. The simulation methodology enables conductive noise aware design for multi-chip mixed-signal PCB in its design stage.