FPGA Implementation of Fuzzy Interpreted Petri Net

The paper introduces new implementation methods of the fuzzy interpreted Petri net (FIPN) on FPGAs. The realization of FIPN is based on fast array multipliers and multipliers utilizing DSP blocks available on FPGA systems. The paper contains descriptions of particular network components’ architectures and results of simulations of these components. In the paper a real control system is designed, which is used to show properties of FIPN. A few slightly different implementations of the example control system as well as their comparison in terms of FPGA resources requirement and calculations speed are also featured. The conducted experiments revealed that the proposed FPGA implementation is many times faster than software realizations of the same control system exercising typical microprocessors and microcontrollers.