Highly reliable poly-SiGe/amorphous-Si gate CMOS

We have developed highly reliable poly-SiGe-gated CMOS devices using a poly-SiGe/a-Si (3 nm) gate structure for sub-0.1 /spl mu/m CMOS devices. It was found that by adding a thin amorphous-Si (a-Si) layer, Q/sub BD/(50%) is improved compared with the conventional poly-SiGe and even with pure poly-Si N/PMOS devices. Furthermore, low gate depletion was obtained for the poly-SiGe/a-Si gate. The polarity dependence of the Q/sub BD/ improvement suggests that the a-Si layer reduces a "weak reliability layer" of SiO/sub 2/ near the SiGe/SiO/sub 2/ interface. Appreciably higher performance of poly-SiGe/a-Si gate N/PMOSFETs was demonstrated compared with conventional poly-Si gate N/PMOSFETs.