Hardware Implementation of DCT/IDCT sharing for HEVC/MPEG Video Coding

The main proposal of this paper is to design hardware sharing architecture for DCT and IDCT between in MPEG-2 and HEVC. Using the common factor of MPEG-2 and HEVC $8\times 8$ DCT coefficients, a mapping technique suitable for hardware design is proposed. Based on hardware design aware, transform coefficient of MPEG-2 is developed by a basis of 2 and added by the compensation coefficient matrix. The transform coefficient ofMPEG-2 and HEVC are verified and can be sharing. We propose a hardware architecture design in FPGA for resource sharing. Its architecture 2D-DCT takes 2424 slice LUTs and the maximum achievable clock frequency for the proposal is 209.732 MHz.