Binary counter with counting period of one half adder independent of counter size

The properties that make a fast counter suitable for many applications are: (1) a high counting rate, independent of the counter size; (2) a binary output that can be read on-the-fly; (3) a sampling rate equal to the counting rate; and (4) a regular implementation suitable for VLSI. The authors describe the implementation of a counter having these properties. The minimum period of the counter is equal to the delay of one half adder plus the delay of loading a flip-flop. Both a modulo-2/sup n/ case and the more general modulo-p cases are considered.<
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