Lowering the Dark Count Rate of SPAD Implemented in CMOS FDSOI Technology

This article presents an optimization study aiming at decreasing the Dark Count Rate (DCR) of Single Photon Avalanche Diodes (SPAD) implemented in CMOS Fully Depleted Silicon-On-Insulator (FDSOI) technology. SPAD realized in standard FDSOI process exhibits high DCR due to high band-to-band tunneling. We show by TCAD simulations associated with some post-processed data that SPAD with much lower DCR (5 orders of magnitudes lower) can be achieved by a single implant modification in the fabrication process.