Reliability-Aware Design Strategies for Stateful Logic-in-Memory Architectures

The in-memory computation of logic operations is a promising paradigm that could enable the development of highly efficient computing architectures, ideal for battery-powered devices. Indeed, Resistive Random Access Memory (RRAM) devices and the material implication logic (IMPLY) have been experimentally demonstrated to enable low-power logic-in-memory (LIM) circuits. Still, device and circuit non-idealities (e.g., the strong sensitivity to driving voltage variations) introduce several reliability challenges that must be addressed with appropriate device models. Often, general-purpose or simplified models are used in the analysis, thus resulting in questionable estimations and designs. In this work, we use a physics-based RRAM compact model, comprehensive of device non-idealities, to study the reliability of IMPLY-based LIM circuits. The analysis is first performed on the single IMPLY logic gate and then extended to an array implementation encompassing the effect of line parasitic resistances and node capacitances. We determine and quantitatively evaluate important metrics such as energy consumption and maximum array size, and derive appropriate design strategies aimed at improving the reliability of such circuits.