On-chip Digital Calibration of Low-Voltage Analog ICs in Nanotechnologies

This work deals with methods of on-chip digital calibration for analog integrated circuits in nanotechnologies. Research and evaluation of existing calibration methods was done at the beginning, followed by the implementation of digital calibration for a variable gain amplifier (VGA) in 130 nm CMOS technology, operating under 0.6 V supply voltage. The purpose of calibration is the cancellation of the VGA input offset voltage V
_IOFF
. The whole design was verified using Monte Carlo analysis and partially also by experimental measurement on 10 packaged chip samples. A student team project was aimed to the automation of the chip measurement process. Measurements of calibrated VGA (cVGA) reveals the V
_IOFF
variation between 13 μV and 823 μV . The calibrated circuit reaches DC gain of 30 dB, which well corresponds with the nominal VGA design. In order to evaluate the calibration effectiveness, measurements include also the VGA samples without calibration, realized in the same technology. The obtained V
_IOFF
reaches μ = 403 μV and σ = 3, 45 mV over 60 unpackaged dies. The paper also proposes ”ping-pong” technique to enable continuous operation of the amplifier.