Development of a Method for Timing Analysis of Reconfigurable System-on-a-Chip Based on Models of Special Logic Elements

In this paper, we propose methods for the timing analysis of circuits implemented in the basis of Reconfigurable System on a Chip (RSoC). The methods are based on the idea of clustering and partial characterization with the subsequent use of static timing analysis tools. RSoC refers to the new VLSI architecture, which contains FPGA-based reconfigurable logic blocks and IP cores, such as RAM, PLL, arithmetic blocks, and others. Partial characterization of a single cell takes time significantly less than the time of usual simulating the entire circuit in an electric simulator. The paper proposes methods of automatic parallelization of the computational process to further accelerate the timing analysis. The experiments demonstrate high accuracy in calculating the time delays of the circuit for an acceptable time, which makes it possible to use it in the task of finding the optimal place and route solution.