Verilog Design of All-Digital Phase-Locked Loop with Two-Cycle Conversion Time-to-Digital Converter

This paper presents an implementation of the All-Digital Phase-Locked Loop circuit in Verilog HDL. It is designed using standard library cells only. NAND cells are the main bricks for all critical paths, which allows balancing values of delays in delay paths. Parameterization of the RTL circuit description allows getting ready for synthesizing circuit with specified characteristics. These leads to a significant simplification of the process of designing SoC in all-digital flow. The presented All-Digital Phase-Locked Loop circuit is based on the Digital Controlled Oscillator entirely built on NAND elements, as well as a 2-level Time-to-Digital Converter, which allows finding the required frequency for two clock cycles of the reference clock.