The Iterative SAT Based Approach to Detailed Routing for Reconfigurable System-on-a-Chip

The paper presents a new iterative Boolean satisfiability (SAT) based approach to the routing of the switch blocks in an island-style reconfigurable system-on-a-chip. The detailed routing procedure results in obtaining the optimal combination of switches, multiplexors or tri-state buffers, inside a switch block. All the assigned interconnections should be completely routed without any conflicts. Within the SAT based approach each actually used switch block is presented as a Boolean equation system that is processed by the SAT-solver. In this paper the detailed routing task is solved for the switch blocks of two architectures. Their main difference is the quantity of tracks the current pin of switch block can be connected to. The computational experiments prove the efficiency of the considered method. The algorithm implemented in C programming language meets the requirements of the netlist full routability and minimization of routing runtime.