A 26-GHz-band High Efficiency Stacked-FET Power Amplifier IC with Adaptively Controlled Load and Bias Circuits in 40-nm SOI CMOS

This paper presents a 26 GHz band high efficiency power amplifier (PA) IC with adaptively controlled load and bias conditions. An adaptively controlled load matching circuit cooperating with an adaptive bias circuit is proposed to achieve a high efficiency PA IC in a broad range of input power. The chip of PA IC is fabricated using 40-nm silicon on insulator (SOI) CMOS process and evaluated on wafer. The fabricated PA IC has shown a peak PAE of 40.2% and a saturation output power (Psat) of 20.5 dBm with a 4.0 V applied voltage on Vdd at 26GHz. A PAE of over 35% at an input power between -2 dBm and 7 dBm has been realized.