Variability-Aware Predictive Modeling of Line-to-Line Dielectric Reliability

We present a predictive model for line-to-line dielectric reliability that takes variability into account. The lifetime distribution is obtained by performing series-parallel reliability computations, starting from the failure distributions of single dielectric unit cells, assumed to be Weibull. The electric field in between the lines is estimated point-by-point, and the power law is applied to account for the related impact on the Weibull scale parameter of every single cell. Finally, the model is calibrated to actual reliability measurements to fix the reference parameters of the Weibull distribution and power law. We employ our model to predict the impact of line-edge roughness (LER), and die-to-die spacing variations on the reliability of scaled interconnects and derive specs from meeting ten years lifetime at operating conditions. We show that specs can be expressed in terms of a single combined-metric, that is, the line-spacing roughness over the wafer (WLSR). Consequently, tradeoffs can be made between specs on LER and die-to-die spacing variations to achieve the same reliability margin. We calibrate our model to Time-Dependent Dielectric Breakdown (TDDB) data from low-k planar capacitors (p-caps) and generate WLSR specs for dimensions ranging from 16- to 8-nm spacing. We predict a significant drop in the reliability margin when scaling down the spacing or the dielectric k-value. As an example, we observe more than 50% reduction in the allowed σWLSR from 16- to 10-nm spacing. We also compare single with multipatterned interconnects. For spacer-assisted multipatterning, spacing edges are cross-correlated, and we predict that for the same die-to-die spacing variations more than two times higher LER is allowed with respect to single patterning to meet the same reliability requirements.