Slewing Mitigation Technique for Switched Capacitor Circuits

Slewing in switched capacitor (SC) circuits reduces the available time for linear settling, and hence increases the nonlinear settling error. This transient demand in current can be supplied by making the bias currents larger in the operational transconductance amplifier (OTA). However, this increases the static power consumption significantly. In this paper a slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to the SC circuit so that OTA does not need to provide high peak current. This may eliminate slewing altogether, and allows using OTAs with less static current for the same settling accuracy. The operation of the proposed technique is illustrated by incorporating it in a second-order delta-sigma modulator (DSM). The modulator was designed and simulated in a 65nm CMOS process. Post-layout extracted simulations with optimized design show more than 12 dB improvement in signal to noise and distortion ratio (SNDR) for the same static power. Alternatively, compared to a DSM without such technique, the same performance can be achieved with 30% less power.