A Two-Step ADC With Statistical Calibration

This paper describes a prototype two-step ADC with adjustable resolution in 40 nm CMOS technology. It uses a front-end successive-approximation-register ADC and a back-end time-domain ADC. Digital statistical calibration overcomes errors from front-end mismatch as well as inter-stage and back-end nonlinearity by analyzing specific statistical properties. In the 12-bit mode at 20 MS/s, the maximum SNDR is 59 dB before calibration and 68 dB after calibration, using 6.2 fJ per conversion-step, excluding the power dissipation required by the calibration.