Design and implementation of sorting algorithms based on FPGA

Analysis of the efficiency of sorting algorithms most often bound up to software simulation. In practical field real time operation needs a system of faster sorting operation because software sorting is less effective. With the advancement of VLSI design sorting algorithm can be easily implemented as a block in any system which can be effectively used when necessary. In this paper, three most common sorting algorithms bubble sort, selection sort and insertion sort algorithm will be implemented using Verilog HDL language. For all algorithms RTL (Register Transfer Level) diagram will be examined and associated timing diagram will be analyzed for worst case scenario. Then the comparative analysis for the algorithms will be given form the analysis and synthesis report and from some operating parameters. The algorithm which has better hardware performance can be used as a block in any system with parallelism.