Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1},2^{n}+2^{n-1}-1,2^{n+1}-1\}$

Residue number systems (RNS) are characterized by fast modular arithmetic and low power dissipation. Numerous RNS applications take advantage of moduli set τ = {2
ⁿ
-1, 2
ⁿ
, 2
ⁿ
+ 1}, with nearly 2
³ⁿ
dynamic range and fast parallel-prefix adders. However, the 2
ⁿ
+ 1 channel is 4ΔG slower (ΔG = simple 2-input gate delay). To remedy such speed imbalance and accommodate higher dynamic ranges, other moduli forms have joined {2
ⁿ
, 2
ⁿ
-1}, with only slightly slower adders (e.g., 2
ⁿ⁺¹
-1 (n = 2
^h
), 2
ⁿ
-2
^q
-1(q <; n - 1), and 2
ⁿ
-3, with at most 2AG more parallel-prefix delay). However, the more the number of moduli, the harder and more costly becomes the required reverse convertor, while otherwise increasing the channel widths n may incur some speed loss. Nevertheless, in the present work, the 3-moduli set τ
⁺
= {2
ⁿ⁺¹
, 2
ⁿ
+2
^n-1
-1, 2
ⁿ⁺¹
-1} is presented, with almost 6× dynamic range than that of the aforementioned τ, where the corresponding parallel-prefix adders are as fast as those for the 2
ⁿ
and 2
^n-1
channels. The required nontrivial forward convertor for modulo 2
ⁿ
+ 2
^n-1
-1 and the reverse convertor for the new 3-moduli set are also designed. Moreover, a new 3-input parallel-prefix node is designed and incorporated, as appropriate for n = 2
^h
, within the employed parallel-prefix networks with the overall advantage of 2ΔG speed-up. Improvements of proposed designs are confirmed via circuit synthesis.