A Fast Prototyping Workflow for Reconfigurable SDR Applications

Nowadays, the level of complexity attained by embedded systems is convoluting the barrier between simulation and implementation. Dealing with complexity requires of new abstraction layers amongst design phases to guide the process from requirements to implementation. Model-based design methodologies offers an effective alternative to address these designs, but existing commercial tools are limited as new implementation technologies appear. This paper addresses this design problem by proposing an architecture and a methodology for fast prototyping of runtime adaptive Software Defined Radio applications on FPGAs. The methodology follows a model-based design approach including hardware-in-the-loop testing using automatic code generation. The processing architecture has been designed so Dynamic Partial Reconfiguration is possible to switch amongst different processing elements seamlessly at runtime. This approach speeds up the response for test iterations in SDR embedded designs going from hours to ten minutes, which is crucial to save costs.