Clocking scheme, Reset Noise Analysis and Reduction Technique for CMOS Image Sensors utilized in Subretinal Implant

A novel approach of on-chip clock generation and reset noise reduction using the charge pump phase locked loop (CP-PLL) for CMOS active pixel sensor cell (APS) used for subretinal implant system is proposed in this work. The dual role of CP-PLL (clock generation and noise reduction) is presented. The noise in both the popular type of pixel design techniques that is 3T and 4T/5T CMOS pixel sensor is analyzed first. Our investigation shows that accommodation of one extra transistor in CMOS-APS helps in reduction of noise i.e. 4T/5T APS are less noisy in comparison with 3T APS. The maximum noise values recorded for both the types of pixel is 740 mV/sqrt Hz and 1.12 V/sqrt Hz respectively. For analysis of noise under different light conditions, five different photon test currents in the range of 50pA-58pA was applied to APS. Utilizing the proposed methodology the noise for highest current value of 58pA is recorded as 0.99mV/sqrt Hz only, which itself shows the success of proposed on-chip clock for CMOS-APS.