Design of Power Efficient Bit Serial Finite Field GF(2m) Multiplier

This paper presents the VLSI implementation of a Bit serial multiplier for multiplication in binary Finite Field GF(2^m) and is based on Shift and Add algorithm. The polynomial base representation is used. The multiplier generates the result by shifting one of the multiplicand. Form bit inputs; it produces output after m-1 clock cycles. The value of m can vary up to 283 bits. Multiplier is designed using Verilog HDL. The designed Multiplier is simulated using NG Spice. The proposed design is synthesized in CADENCE Encounter. Using the low power VLSI methodology power consumption is reduced. Proposed multiplier is implemented using CADENCE virtuoso tool set using GPDK45nm technology.