Error-Aware Design Procedure to Implement Hardware-Efficient Logarithmic Circuits

State-of-the-art accurate logarithmic circuits involve shift-and-add operations which demand a high area cost. In this brief, a design procedure to implement a hardware-efficient logarithmic circuit is proposed which eliminate the use of shift operations. Logarithmic function curve is approximated using multiple regions of unity slope straight lines by adjusting the intercepts. The proposed procedure determines the number of regions and the corresponding intercepts to implement logarithmic circuit for a desired error constraint. Six logarithmic circuits were realized using the design procedure which exhibited maximum absolute error of 0.029, 0.0175, 0.0083, 0.0026, 0.0021 and 0.00179. The designs were synthesized using 65nm CMOS technology. The proposed designs showed up to 83.60%, 91.76% and 94.56% reduction in energy, energy-delay product and area-delay-power product when compared with those of state-of-the-art logarithmic circuits of comparable error.